The present disclosure relates generally to semiconductor devices, and more particularly, to a circuit for controlling an initializing circuit in a semiconductor device.
Generally, in semiconductor devices, all the devices are initialized by a power-up signal generated when the power is on. A timing diagram of an initializing Joint Electron Device Engineering Council (JEDEC) standard sequence is shown in FIG. 1. FIG. 2 is an enlarged view of a circular dotted portion xe2x80x98Axe2x80x99 in FIG. 1. In FIG. 2, slant lines represent don""t care regions. In a rectangular dotted region in FIG. 2, even after VDD is increased, only CKE (CLOCK ENBLE) is specified as a LVCMOS LOW level. Other CLK (CLOCK), COMMAND, ADDRESS and Vref are specified as a don""t care. That is, the don""t care region means that CLK can enter it, Vref may be a LOW level, and any of ADDRESS and COMMAND can enter to the device. In other words, there will be a case where the device erroneously operates because of the don""t care region even though VDD is raised in the initial process.
An example of erroneous operation of the device will be examined by reference to FIGS. 3 and 4. FIG. 3 is a circuit diagram of a circuit for receiving a clock enable signal (CKE) including a differential amplifier. This circuit compares the reference voltage (Vref) and the clock enable signal (CKE) to produce an output (net1). It is not a problem when a NMOS transistor is down when the reference voltage (Vref) is higher than the threshold voltage of the NMOS transistor. However, if the reference voltage (Vref) is lower than the threshold voltage of the NMOS transistor, a case where the potential operation within the NMOS transistor could not be expected because CLK, COMMAND and ADDRESS are in the don""t care condition.
In particular, a read operation and an erroneous mode register (MRS) setting are most concerned. An erroneous read operation command not only causes an erroneous read operation but also outputs a data output (DQ) and a data clock (DQS), which results in unnecessary power being consumed.
As shown in FIG. 4, if MRS setting was wrong and all of CAS latency (CL2 through CL4) became LOW states, the output (net1) is floated. In this state, if the output (outen) of the inverter becomes a HIGH state depending on a state of surrounding lines, unwanted and/or unnecessary read operation, etc. is performed that consumes power.
A circuit for controlling an initializing circuit is described. The circuit may prevent power consumption because of unnecessary operation, in which a power-up signal that gives an initial value at an initial state is kept at a LOW state until a first NOP operation, and the power-up signal is then performed after CLK, COMMAND, ADDRESS and Vref are internally normally set.
The circuit for controlling an initializing circuit comprises a first circuit configured to generate a NOP operation command signal, and a second circuit configured to maintain a power-up signal to a LOW state until the NOP operation starts and to shift the power-up signal to a HIGH state depending on the NOP operation command signal.
The first circuit comprises a PMOS transistor connected between the power supply and a first node and responsive to a write enable signal, a first NMOS transistor connected to the first node and responsive to a row address strobe signal, a second NMOS transistor connected to the first NMOS transistor and responsive to a column address strobe signal, a third NMOS transistor connected to the second NMOS transistor and responsive to the write enable signal, a fourth NMOS transistor connected between the third NMOS transistor and the ground, an inverter configured to invert the potential of the first node, and a second PMOS transistor in parallel connected to the first PMOS transistor and responsive to an output of the inverter.
The second circuit comprises a NAND gate having first and second input terminals, wherein the power-up signal is inputted to the first input terminal. The second circuit also comprises a transmission gate configured to transfer the power-up signal to the second terminal of the NAND gate depending on the NOP operation command signal, a first inverter configured to invert an output of a NAND gate, and a second inverter configured to invert the output of the NAND gate to supply the inverted output to the second input terminal of the NAND gate.